1. Field of the Invention
This invention relates to a CPU emulation system, a CPU emulation method, and a recording medium having a CPU emulation program recorded thereon. In particular, this invention relates to a CPU emulation system, a CPU emulation method, and a recording medium having a CPU emulation program recorded thereon, which are capable of performing, with the use of a multiprocessor, optimization processing of an instruction sequence without delaying instruction sequence execution processing.
2. Description of the Related Art
A CPU emulation system is a system for software-emulating a physical CPU to implement, as a virtual CPU, a CPU having an instruction set architecture (ISA) different from that of the physical CPU. The virtual CPU reads an instruction sequence for the ISA, which is manageable by the virtual CPU, and, after translating the read instruction sequence into an instruction sequence executable on the physical CPU, executes the translated instruction sequence.
As such a CPU emulation system, Japanese Unexamined Patent Application Publication (JP-A) No. 2002-312180 A (Hereinafter, referred to as Patent Document 1) discloses a CPU emulation system that uses a multiprocessor.
In the CPU emulation system including a plurality of processors described in Patent Document 1, processing of prefetching an original instruction, processing of interpreting and executing an original instruction sequence, and processing of translating and optimizing an instruction sequence are each executed on a different CPU. By separating a CPU for executing an instruction sequence from a CPU for performing optimization of the instruction sequence in this manner, the optimization processing of the instruction sequence is made to have no adverse effect on processing throughput of the instruction sequence execution processing.
Further, Japanese Unexamined Patent Application Publication (JP-A) No. 2004-110824 (Hereinafter, referred to as Patent Document 2) discloses an instruction sequence optimization system that uses a multiprocessor. According to Patent Document 2, with regard to a program that is being executed on one CPU, profile information thereon is collected, and, based on that information, the instruction sequence is optimized on another CPU during the execution. By separating a CPU for executing an instruction sequence from a CPU for optimizing the instruction sequence in this manner, the optimization processing of the instruction sequence is made to have no adverse effect on processing throughput of the instruction sequence execution processing.